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Beckhoff ET1810, ET1811, ET1812
The EtherCAT IP core enables the EtherCAT communication function and application-specific functions to be implemented on an FPGA (field programmable gate array, an integrated circuit containing progra…
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Description
The EtherCAT IP core enables the EtherCAT communication function and application-specific functions to be implemented on an FPGA (field programmable gate array, an integrated circuit containing programmable logical components). The EtherCAT functionality
Specification
| Phy Interface | 1…4 ports MII, 1…4 ports RGMII or 1…4 ports RMII |
|---|---|
| F M M Us | 0…16 |
| Sync Manager | 0…16 |
| D P R A M | 0…60 KB |
| Distributed Clocks | 0…4 SYNC outputs, 0…4 latch inputs (32/64 bit) |
| Process Data Interfaces | PDI0: 32 bit digital I/O, SPI slave, 8/16/32 bit asynchrones µC-Interface, Avalon interface, AMBA AXI4 interface. PDI1: 32 bit digital I/O, SPI slave, Avalon interface, AMBA AXI4 interface. 64 bit general purpose I/O |
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